Hazard Detection Tool in Asynchronous Finite State Machines Transition Logic
DescriptionThe presence of hazards in asynchronous circuits is especially critical since glitches can cause unwanted transitions.
Therefore, the AFSM generation flow our team developed must guarantee that hazards inside AFSM logic are detected and glitches avoided.
Hazards could be identified through random simulations, but they require an extremely long testing time. Besides, they are usually carried out only at the last steps of the design when it is too late to make significant design changes.

A "Hazards Detection Tool” has been implemented to detect the hazards present in the AFSM arc transitions logic. The tool analyzes an AFSM design file containing the arc transition's logic expressions and writes a text file with the list of all the hazards found in their implementation.
Starting from this hazard list a testbench is produced for an early debug.

This solution can be implemented using commercial tools such as Cadence's Xcelium for simulation. It cuts down testing time and let the user focus on simulating critical cases. These simulations allow to study how the rest of the asynchronous circuit behaves in case of a glitch.
Event Type
Engineering Track Poster
TimeWednesday, July 12th5:32pm - 5:33pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design