Presentation
Is your structural CDC sign-off complete?
DescriptionThe verification paradigm of having simulation-based environment for every corner case has already taken halt in 1990s. The field of static analysis by structures and associated constraints has helped in signing off major concerns like asynchronous clock driven logic boundaries and associated problems. Nowadays Clock Domain Crossing aka CDC is a general practice or QA checklist item for IP signoff. But this approach heavily rely on assumptions. These assumptions are of two kinds: 1. Protocol assumptions, which assumes if receiving pulse will be always wide enough to cross async boundary, if data will remain stable when control is enabled and most importantly no incoherency among FIFO pointers or synchronizers. 2. Constraints which are provided for structural signoff like static/stable signal, constants and mutually exclusive signals will hold true in actual design mode operation.
These assumptions demand stimulus-based input for actual scenario signoff. Therefore, for reliable signoff there arises a need for some link between static and simulation-based verification.
The first two in protocol assumptions are usually checked in verification environment, but incoherency detections requires strong link with static verification where right set of synchronizers participating in deep convergence can be identified statically and verified in simulation.
Moreover, CDC static signoff can be localized to IPs but simulation verification could be on higher abstraction like SoC or subsystem level. This necessitates the flow to have multiple CDC units having protocol and constraints assumptions to be bound together and verified simultaneously in single simulation environment.
In this presentation we will discuss the case study of an exhaustive methodology and bugs caught for reliable signoff on async designs with async crossings.
These assumptions demand stimulus-based input for actual scenario signoff. Therefore, for reliable signoff there arises a need for some link between static and simulation-based verification.
The first two in protocol assumptions are usually checked in verification environment, but incoherency detections requires strong link with static verification where right set of synchronizers participating in deep convergence can be identified statically and verified in simulation.
Moreover, CDC static signoff can be localized to IPs but simulation verification could be on higher abstraction like SoC or subsystem level. This necessitates the flow to have multiple CDC units having protocol and constraints assumptions to be bound together and verified simultaneously in single simulation environment.
In this presentation we will discuss the case study of an exhaustive methodology and bugs caught for reliable signoff on async designs with async crossings.
Event Type
Engineering Track Poster
TimeTuesday, July 11th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V