Presentation
Design For Testability in Asynchronous Digital Controllers : An automated flow to design and validate asynchronous logic for digital controllers
DescriptionHigh performance digital controllers for analog IPs can be implemented with asynchronous logic designs. The main applications are Power Management IC and analog IPs designed with switched capacitor circuits which needs a peculiar driving of phases to reach required performance.
Since the complexity of these digital controllers is increasing, and Automated Test Pattern Generation (ATPG) with EDA tools is not able to reach high coverage for this kind of logic, a custom automated flow has been developed in order to add the DFT to such kind of designs, enabling the controllability and the observability of the circuit during test phase, in particular for stuck-at faults detection.
Once the scan-chain based architecture is built, the tool generates the patterns to be inserted and the values to be checked after the capture phase. These patterns are then used by the Product Engineer.
This approach has been successfully applied to a large number of designs, resulting in a fully automated design flow for asynchronous digital controllers.
Since the complexity of these digital controllers is increasing, and Automated Test Pattern Generation (ATPG) with EDA tools is not able to reach high coverage for this kind of logic, a custom automated flow has been developed in order to add the DFT to such kind of designs, enabling the controllability and the observability of the circuit during test phase, in particular for stuck-at faults detection.
Once the scan-chain based architecture is built, the tool generates the patterns to be inserted and the values to be checked after the capture phase. These patterns are then used by the Product Engineer.
This approach has been successfully applied to a large number of designs, resulting in a fully automated design flow for asynchronous digital controllers.
Event Type
Engineering Track Poster
TimeTuesday, July 11th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V