Presentation
A Digital Emulator for an Analog Continuous Time Sigma Delta Modulator
DescriptionModern high precision, low power Sigma Delta Modulators are used in ADCs for multiple applications including 5G, Radar, Software Radio. The development time for such high-performance analog blocks is usually high because of large simulation times, even at modelling stage. The problem is exacerbated when the Sigma Delta Modulator design is in Continuous Time (CTSD) as discrete sampling nodes disappear. Co-simulation of the analog modulator with a digital assist hardware becomes very challenging as digital calibrations take a long time. We propose a method no numerically model the analog Continuous Time Sigma Delta Modulator (CTSD) op-amp based integrators as an oversampled digital system. The proposed emulation method is a radical approach that demonstrates speeds up simulation and analyses of CTSD modulator by orders of magnitude. An inverse Laplace of the analog integrator transfer function is discretized using Euler's Backward Method. The discretized continuous time modulator circuit is realized in VHDL and is implemented on an FPGA. The proposed method can be used to model and discretize many other analog blocks in digital to achieve very high speed emulation and thus drastically reduce design cycle time.
Event Type
Engineering Track Poster
TimeTuesday, July 11th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V