Design and Verification of AXI4 Master for ASIC using High Level Synthesis in C++
DescriptionDesigning a direct memory access (DMA) block which meets bus protocol specifications such as AMBA AXI can be time-consuming. Nonetheless, its reusability is limited when designed in RTL since many parameters such as data bus width can vary over a wide range (i.e., 8-bits to 1024-bits), making it difficult to synthesize using the same code. To tackle this issue, we designed AXI4 master IP which meets full AXI4 specifications using C++ HLS, providing software-like access to DMA blocks, while achieving high throughput using multiple outstanding and burst. Thanks to C++ templates, RTLs can be extracted from the same C++ code with different template arguments, supporting various address and data bus widths. After the design and verification of the IP in high level, we verified the extracted RTL and checked if the result matches the C++ test. Finally, it was applied to our automotive vehicle control processor (MCU, Samsung 28nm), NPU-based ADAS processor (N-Dolphin, Samsung 14nm), and automotive application processor (Dolphin 5, Samsung 8nm), and verified with post-silicon.
Engineering Track Poster
TimeTuesday, July 11th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall