Efficient methodologies for STL certification of Spinoff SOC designs.
DescriptionGiven the increasing application of processors in automobile systems, we need to provide a self test library (STL) to our customers to meet safety goal.
A STL is a software work product that helps the customer identify a certain percentage of Hardware faults in a processor core. This percentage is called the Diagnostic Coverage(DC).
These test vectors need to be tested in simulations in every SOC spin to ensure that the vectors can detect the required number of faults to meet our safety goal. We have observed that the STL fault injection, along with tailoring the STL for the latest SOC is a time consuming process. We needed a way to gain a high confidence about future SOC compatibility. Streamlining this process can shorten certification time for spinoff designs.
Secondly, we need to eliminate several safe faults from fault scope to be able to obtain our claimed DC. Due to the subjective nature of safe faults and the difficulty in analyzing a netlist , it becomes very difficult to ascertain and annotate this "safe” logic accurately and quickly. We needed a scalable methodology to address this.
This paper explores these challenges and the innovative solutions used to solve them.
Event Type
Engineering Track Poster
TimeWednesday, July 12th5:26pm - 5:27pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design