Presentation
Automation Framework Based IP/Subsystem Integration Verification in SoC - A Systematic Approach for Integration Quality Signoff
DescriptionIn this catalogue market era, SoCs are more generic to cover multiple end applications, so a typical SoC may contain 10s or 100s of sub-systems / IP instances integrated together. Each IP / sub-system by itself can have 100s or 1000s of ports which gets connected across in the SoC. These modules may be designed independently and when integrated, there can be common mismatches (BUGS) which could cause malfunction in the SoC. Ensuring integration correctness of all modules is critical to achieve early bug findings and on-time systematic verification closure. Writing these integration checks manually for all the ports of all modules in an SOC consumes time and viable to manual error / miss / late findings in the design cycle. In this paper we discuss a systematic approach to auto generate all integration checks across all ports for all IPs/subsystem in an SoC to verify integration correctness and module-module handshake assumptions or protocol interfaces. This enhances verification efficiency and helps in early bug findings in the design cycle. This also provides a method to signoff integration RTL and test quality with assertion coverage of integration correctness using FV and simulation approaches.
Keywords: Integration signoff, Assertions, MDV, Coverage
Keywords: Integration signoff, Assertions, MDV, Coverage
Event Type
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
TimeMonday, July 10th5:16pm - 5:24pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP