Presentation
Static Analysis for Early Detection and Efficient Debug
DescriptionAlif Semiconductor develops scalable processors designed to connect and process systems in an
affordable and productive manner. Alif's ICs are often many millions of gates, with hundreds of
clocks, and a multitude of IP blocks. Given the extraordinary cost of a re-spin, much effort has gone
into establishing a comprehensive and efficient functional verification flow.
Alif has adopted a verification flow that incorporates simulation-based and formal as well as static
analysis tools. The static analysis tools serve two objectives: sign-off of targeted aspects that are
difficult and inefficient to verify with simulation, and fast & easy detection of fundamental issues.
Alif's flow uses Real Intent static tools to sign off on critical aspects of the functionality – specifically
multi-mode clock & reset metastability. They also use Real Intent's Lint and DFT tools to catch IP
integration issues and to instill confidence in the IP early in the flow. Static analysis tools offer very
precise debug information for quickly resolving issues.
This paper focuses on the benefits of using CDC, Lint & DFT checking throughout Alif's flow.
Examples of issues detected as well as the simplicity of debug that makes it fast & easy to resolve
fundamental issues early.
affordable and productive manner. Alif's ICs are often many millions of gates, with hundreds of
clocks, and a multitude of IP blocks. Given the extraordinary cost of a re-spin, much effort has gone
into establishing a comprehensive and efficient functional verification flow.
Alif has adopted a verification flow that incorporates simulation-based and formal as well as static
analysis tools. The static analysis tools serve two objectives: sign-off of targeted aspects that are
difficult and inefficient to verify with simulation, and fast & easy detection of fundamental issues.
Alif's flow uses Real Intent static tools to sign off on critical aspects of the functionality – specifically
multi-mode clock & reset metastability. They also use Real Intent's Lint and DFT tools to catch IP
integration issues and to instill confidence in the IP early in the flow. Static analysis tools offer very
precise debug information for quickly resolving issues.
This paper focuses on the benefits of using CDC, Lint & DFT checking throughout Alif's flow.
Examples of issues detected as well as the simplicity of debug that makes it fast & easy to resolve
fundamental issues early.
Event Type
Back-End Design
Embedded Systems and Software
Engineering Track Poster
Front-End Design
Gladiator Area Poster Battle
IP
TimeMonday, July 10th5:32pm - 5:40pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP