Presentation
High-Performance Design with Rapid RTL Profiling of Critical Power Scenarios
DescriptionAs SoCs grow more complex each generation, their transistor count, board size and power demand increase as well. When an incoming workload results in activation of many parts of an SoC at the same time, a large amount of current gets drawn, which can cause significant voltage drops in the power grid. These drops can cause the voltage-frequency curve to shift, causing maximum frequency to decrease and hence degrade chip performance.
To mitigate the problem, early detection of such activities is needed.
Traditionally, one can use cycle-based power simulations where current for each clock cycle is reported and then one can see where the problem is. However, such simulations are very time consuming and unrealistic for real case scenarios.
The solution is to use a new rapid RTL based power profiling simulation methodology to understand when relatively high power is observed across long vectors. Afterward, the traditional methodologies can be used to accurately calculate the magnitude of those power-critical events and drive power grid and other design decisions.
To mitigate the problem, early detection of such activities is needed.
Traditionally, one can use cycle-based power simulations where current for each clock cycle is reported and then one can see where the problem is. However, such simulations are very time consuming and unrealistic for real case scenarios.
The solution is to use a new rapid RTL based power profiling simulation methodology to understand when relatively high power is observed across long vectors. Afterward, the traditional methodologies can be used to accurately calculate the magnitude of those power-critical events and drive power grid and other design decisions.
Event Type
Engineering Track Poster
TimeWednesday, July 12th5:33pm - 5:35pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V