Ultra-Low Voltage Enablement for Standard Cells with Moment based LVF
DescriptionSTMicroelectronics provides digital IPs, including standard cells and memory IPs for use by various applications including IoT, automotive and artificial intelligence. Accurate implementation of digital designs to manage the variability of these IPs is essential to achieve high silicon yield maintaining power, performance, and area requirements of the target SoC.
Digital designs can no longer rely on simple flat margins/derates with OCV (On Chip Variation) based flow to perform signoff. For low power applications, where supply voltage is being scaled (especially when it approaches close to threshold voltage of device) to minimize dynamic and leakage power consumption, the delay values no longer remain Gaussian attributed to large statistical variation. In this paper, we have demonstrated the study of delay variation on several standard cells at lower voltages by comparing reference Spice simulation from Eldo with fast Monte-Carlo (SSD) like approach to generate LVF and extending it to moment based LVF. Further, Primetime has been used to analyze cell behavior scalability with reference Spice. Finally, as proof of concept, critical path analysis has been done with Spice as well as Primetime to demonstrate the accuracy achieved in delay scaling at those low voltages.
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall