Paradigm Shift in Power Aware Simulation Using Formal Techniques
DescriptionExhaustive verification of power aware connectivity and functional properties using formal verification tools is required to shift left the simulation-based power verification flow

Traditional power aware simulation tools can be used but require additional power sequence tests in testbench which is expensive, and do NOT guarantee exhaustive verification

Thus, power aware formal verification is the need of the hour to shift left the functional verification flow to significantly reduce the overall TAT

Power aware formal property describes a connection in which verification flow uses power network model (PNM) from VC LP and exhaustive analysis engines of VC-Formal to prove correctness of properties

This solution introduces a lightweight PNM which is dumped in a Synthesizable Verilog format which generates functional model of UPF supplies considering
1. Power Switches
2. Fine grain macros
3. Power Down Functions (PDF)
4. Power states (add_power_state)
5. Resolution functions etc.

PNM helps to capture the FULL_ON/OFF state modeling for different supplies specified in the UPF and is directly consumed by the formal tool to verify the power aware properties through corruption MUXes and minimal instrumentation
Event Type
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design