Advanced transceiver components for robust handling of signal noise and loss
DescriptionThere is tremendous growth in information traffic with the digital transformation of businesses. The wide adoption of cloud has driven substantial demand for fast access to data. The number of hyperscale data centers continues to grow rapidly. The end-to-end Information traffic from enterprise data center to cloud data center, to Edge, to 5G infrastructure requires transceiver interfacing that provide the gateway into, within, between and out of chips. Depending on the application, different high-speed links support different range of data rates and protocols employing complex modulation schemes and varying insertion loss requirements from Very Short Reach (VSR) at few dBs to Long Reach (LR) at 35+ dB. Furthermore, the network traversal requirements with backplane, cable, or optical media spans from a few inches to tens of kilometers, and from within data center to outdoor in harsh environment. The diverse applications and requirements of SerDes poses design challenges for accurate data and clock recovery with stringent jitter requirements requiring innovative equalization architectures to compensate for channel loss, distortion and cross talk.

eTopus Technologies is a US based start-up with world-wide design centers developing ultra-high speed mixed-signal semiconductor solutions for HPC, data center, networking, storage, 5G and AI applications. eTopus has demonstrated multiple generations of ADC/DSP-based PAM-4 SerDes IP to support multiple data rates such as PCIe Gen6 64Gbps and Ethernet 56Gbps/112Gps from 28nm CMOS planar through 6nm FinFet process technologies with superior BER performance and continue to develop future generation designs with 224Gbps PAM-N as the next target.

eTopus uses Siemens EDA's Analog FastSPICE Platform (AFS) for circuit verification and sign-off. To meet or exceed quality requirements with faster time to market, an accurate, fast and versatile simulator is required to handle various netlist constructs (schematic and extracted including S-Parameters) for functional, test and reliability analyses. With AFS, designers can experiment, and finalize analog circuits of varying sizes with DC, AC, transient, transient noise and RF analyses to create robust transceivers, with augmented support of other Siemens EDA front and backend verification software.

In this paper, we provide an overview of differentiated ADC DSP based SerDes components. We will showcase simulation correlated to silicon measurements of eTopus's SerDes designs, including CTLE performance metrics for 56Gbps in 16nm and 13.28125GHz clock paths and signal integrity compliance for 106.25Gbps in 7nm.
Event Type
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design