Presentation
Addressing Common Verification Pitfalls of Chiplet Interconnects
DescriptionWith the advent of a range of High-performance computing and Artificial Intelligence (AI) based applications, the need for scalable and affordable optimum-performance computing has exploded in recent years. Leaders of the VLSI design industry have been experimenting with innovative Die disaggregation technologies, enabling a future where a catalog of Chiplets will be available to mix and match based on the end application.
This demands addressing a host of complicated challenges especially Die-to-Die interconnect
This paper focuses on the common design verification pitfalls in the fastest emerging industry standard called Universal Chiplet Interconnect Express (UCIe), which enables end users to use a combination of Chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips
UCIe is a multi-layer, multi-protocol with defined interfaces for Adapter and Phy. On the one hand, interoperability with other pre-defined and well-established protocols like PCI Express (PCIe) and Compute Express Link (CXL), and on the other hand, the possibility to support any other protocol in streaming mode is wide and open.
The paper suggests an effective strategy to optimize effort and improve productivity in the verification using Chiplet-like reusable verification components as a vehicle to demonstrate all possible verification topologies.
This enables shift-left and continuous verification from IP, SOC to System level.
This demands addressing a host of complicated challenges especially Die-to-Die interconnect
This paper focuses on the common design verification pitfalls in the fastest emerging industry standard called Universal Chiplet Interconnect Express (UCIe), which enables end users to use a combination of Chiplets with different functionality and technology nodes to develop highly sophisticated electronic chips
UCIe is a multi-layer, multi-protocol with defined interfaces for Adapter and Phy. On the one hand, interoperability with other pre-defined and well-established protocols like PCI Express (PCIe) and Compute Express Link (CXL), and on the other hand, the possibility to support any other protocol in streaming mode is wide and open.
The paper suggests an effective strategy to optimize effort and improve productivity in the verification using Chiplet-like reusable verification components as a vehicle to demonstrate all possible verification topologies.
This enables shift-left and continuous verification from IP, SOC to System level.
Event Type
Engineering Track Poster
TimeTuesday, July 11th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V