Presentation
Overcoming Challenges in Functional Verification of Automotive Traffic Schedulers
DescriptionThe automotive industry is going through disruptive transformations owing to recent trends in comfort, connectivity, autonomous driving, security, and infotainment. All this drives the need for newer protocols and the next generation of existing protocols. A protocol like Ethernet that has been proven for more than 40 years now, despite having all the required attributes like speed, suitability, scalability, compatibility, and cost-effectiveness, has been evolving by getting Time-sensitive extensions. Capabilities like guaranteed and time-bounded delivery have made it easy to predict the worst-case latency of a network. This has made Ethernet best suited for real-time, mission-critical applications like In-Vehicular communication, Factory Automation, and Industrial control. It opened ways to move from multi-technology protocols LIN, CAN, FlexRay, MOST and single wiring technology for networking in a car. Consequently, new algorithms like CBS, TAS, ATS have come up to schedule and shape traffic in a connected car to handle the Quality-of-Service (QoS) requirements of various traffic classes. Checking the functional correctness of the new category of traffic schedulers is an entirely new verification challenge. The shaping algorithms are mostly receiver agnostic as the receiver has no knowledge of the traffic class, priorities, or algorithm the Transmitter uses to shape the traffic. This makes verification an exceedingly challenging task. Success criteria for verifying these protocols are successful reception of the packets and meeting the latency constraints, bandwidth-over-time, and lower tolerance for timing accuracy. As a result, a simulation cannot ensure the entire verification for these protocols. We chose Credit Based Shaper (CBS) as a case study to resolve challenges faced in Functional Verification of Traffic Schedulers and Shapers. It led to enhancing the Ethernet Receive path, making it feasible to record desired data for creating relevant plots in System Performance Analyzer.
Event Type
Engineering Track Poster
TimeWednesday, July 12th5:49pm - 5:50pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V