Presentation
Fast and Reliable IO Ring Checker for Ensuring ESD Robustness and Power Integrity Compliance of SOC design
DescriptionConstructing an IO Ring/Section that adheres to the IO provider's integration guidelines is key to the Silicon Success of any SOC. The guidelines are generally part of the IO data books and requires very good expertise to implement them as intended.
SOC designers rely on in-house ESD/IO experts or the IO IP providers to manually review their IO rings to avoid any surprise at a later stage of implementation or any silicon failure. This manual activity is error prone. There is a strong need to have an automated tool to check for the proper implementation of the integration guidelines, especially in advanced technologies and in chips with large pin count.
We are presenting ‘IO Ring Checker', an automated way to check all the IO ring integration requirements.
SOC designers rely on in-house ESD/IO experts or the IO IP providers to manually review their IO rings to avoid any surprise at a later stage of implementation or any silicon failure. This manual activity is error prone. There is a strong need to have an automated tool to check for the proper implementation of the integration guidelines, especially in advanced technologies and in chips with large pin count.
We are presenting ‘IO Ring Checker', an automated way to check all the IO ring integration requirements.
Event Type
Engineering Track Poster
TimeMonday, July 10th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design
IP
RISC-V