IO Designs for reliability in advanced technology nodes
DescriptionInput-Output Blocks (IOs) are one of the essential and critical blocks in any SoC. It needs to interact with other chips which can operate at different voltages. Thus, there is a requirement to design IO operating at higher voltage even if the technology is scaling down. While in advanced technology nodes, the gate oxide breakdown limit is also scaling. So, there is a need to design IO operating at high voltage using low voltage devices which brings in the challenge of reliability of the devices used in the circuit. The post-layout parasitic effects in the latest technologies further make design reliability more challenging.
The paper discusses key IO Design reliability challenges and presents an effective IO reliability validation methodology. The design challenges are related to how conventionally used stacked architectures, Receiver/Driver architectures and fail-safe / fail-tolerant architectures are susceptible to reliability concerns. The proposed validation methodology will assist in unearthing reliability concerns in the early design phase. This will lead to a robust design, reduces field failure and improves safety which is critical due to the increasing usage of electronic components in all aspects of life.
Event Type
Engineering Track Poster
TimeWednesday, July 12th5:41pm - 5:43pm PDT
LocationLevel 2 Exhibit Hall
Back-End Design
Embedded Systems
Front-End Design