An Efficient and Spice Aligned Method for Complex IO's Behavioral Model Generation and Verification
DescriptionIncreasing chip complexity and emerging system on chip (SOC) leads to the adaptation of reusable intellectual property (IP) cores. Hardware Description language (HDL) provides the ease to reuse the IP and a developed methodology to link the different IPs smoothly with the core design. But most of the time, Input/Output circuits (IOs) placed at periphery of IC, are not reusable in different design due to different requirements. Due to lack of reusability ease, need of Verilog generation of IO circuits rises every time with new IC design flow. Currently, Verilog generation and verification is a manual process due to absence of automated generation/verification flow for IOs. Manual verification always has probability of error. Moreover, when the design complexity increases, the manual approach of verification seems too tiring and inefficient. This paper introduces a methodology to support automated flow for Verilog generation and complete verification of IO designs as well as checking the equivalence with the schematic design using the spice simulations.
Engineering Track Poster
TimeWednesday, July 12th5:12pm - 5:13pm PDT
LocationLevel 2 Exhibit Hall