Accurate Behavioral Modeling Technique for Simultaneous Active Multiple LVDS Line Driver
DescriptionIn asynchronous peer-to-peer serial links, contention between link partners is possible at the start of the communication. Electrically contention happens at the interface of the link partners. These contention cases are critical and should be verified thoroughly at the system level by the SoC verification engineers. So, to enable thorough verification, the behavioral Verilog model of a full custom-designed interface block should also be accurate and comprehensive. This paper covers an accurate Real Number Modelling(RNM) technique for one of the commonly used interface standards, Low Voltage Differential signaling(LVDS).
Engineering Track Poster
TimeTuesday, July 11th5:00pm - 6:00pm PDT
LocationLevel 2 Exhibit Hall