Presentation
A Joint IP XACT/RTL Design Flow for Large SoC
DescriptionDefacto’s customer challenge was to improve the current IP integration methodology to be able to efficiently align all together large IPs of different formats and views without manual intervention.
There was no solution in the market to make the integration considering jointly RTL and IP-XACT. Workaround was to either redesign IP dropped advance System Verilog construct for datatype and use of package to align with what IP-XACT 2014 can support or making connection pin to pin. Such a workaround is tedious, risking of breaking existing design, time consuming and hard to maintain.The Defacto-based design methodology helped simplify RTL integration flow without changing IP designs and without extra coding in the flow to handle information that's not defined in IP-XACT 2014. The scalability of the solution also brings high transferability across different designs. With simple API interactions, the overall scripting process to integrate the features into the customer flow is smooth. The presented solution has proven its reliability and optimized performance based on the presented SoC projects and is now used in several divisions.
There was no solution in the market to make the integration considering jointly RTL and IP-XACT. Workaround was to either redesign IP dropped advance System Verilog construct for datatype and use of package to align with what IP-XACT 2014 can support or making connection pin to pin. Such a workaround is tedious, risking of breaking existing design, time consuming and hard to maintain.The Defacto-based design methodology helped simplify RTL integration flow without changing IP designs and without extra coding in the flow to handle information that's not defined in IP-XACT 2014. The scalability of the solution also brings high transferability across different designs. With simple API interactions, the overall scripting process to integrate the features into the customer flow is smooth. The presented solution has proven its reliability and optimized performance based on the presented SoC projects and is now used in several divisions.
Event Type
Front-End Design
TimeTuesday, July 11th2:45pm - 3:00pm PDT
Location2010, 2nd Floor
Front-End Design