Presentation
Power Intent Automation for Ultra Low Power Mixed-Signal SoC
DescriptionState of the art low power System on Chip (SoC) design involves extensive manual effort in capturing the low power intent (PI) in a specific machine readable format (either CPF or UPF). With an agile workflow and IPs maturing in parallel with SoC involving several staggered IP releases and different maturities, there are lots of iterations of this manual effort.
This paper highlights an automation flow to generate the PI in CPF format, by auto-deriving relevant information from RTL design, IP deliverables and a machine readable power concept information (in spreadsheet format currently). The power concept information is manually captured by the system integrator in a predefined, intuitive and user friendly template based on the system level power concept.
The automation scripts were developed, and applied on to a highly power managed industrial low power, mixed-signal, embedded processing SoC resulting in >85% reduction in manual effort and cycle time. Further, it improves the quality of power intent and avoids iterations due to manual errors.
It also enables early design verification of hard IPs in SoC context, and flat STA which further improves both quality and time to market.
This paper highlights an automation flow to generate the PI in CPF format, by auto-deriving relevant information from RTL design, IP deliverables and a machine readable power concept information (in spreadsheet format currently). The power concept information is manually captured by the system integrator in a predefined, intuitive and user friendly template based on the system level power concept.
The automation scripts were developed, and applied on to a highly power managed industrial low power, mixed-signal, embedded processing SoC resulting in >85% reduction in manual effort and cycle time. Further, it improves the quality of power intent and avoids iterations due to manual errors.
It also enables early design verification of hard IPs in SoC context, and flat STA which further improves both quality and time to market.
Event Type
Front-End Design
TimeMonday, July 10th4:00pm - 4:15pm PDT
Location2010, 2nd Floor
Front-End Design