Presentation
Sophisticate Performance Verification Of SOC BUS By IP-XACT And Model
DescriptionThere is a need for a method of measuring the performance of BUS topology to secure the chip of performance designed at the architecture stage. To ensure high-performance SOC chips, sophisticated performance verification methods of BUS and memory controllers are required. We are proposing the process to directly compare the systemC model performance (reference) and BUS RTL performance (DUT) by using same the traffic pattern and test point for RTL and SystemC model.
Using the IP-XACT and TG (Traffic generator) configuration automation, TG insertion and configuration are done without human manual operation. The reduced human error allows the performance of the SOC bus to be verified at an early stage and the TAT to be reduced.
The result of DUT (BUS Fabric RTL) can be directly compared to that of model within an error of less than 5% which give high reliability. Performance bugs related to BW and latency have been detected through the process, and it helps to design a performance-satisfied SOC. As a conclusion, A precise methodology for measuring the performance of BUS topology has been developed by directly comparing the performance results of the SystemC model and RTL.
Using the IP-XACT and TG (Traffic generator) configuration automation, TG insertion and configuration are done without human manual operation. The reduced human error allows the performance of the SOC bus to be verified at an early stage and the TAT to be reduced.
The result of DUT (BUS Fabric RTL) can be directly compared to that of model within an error of less than 5% which give high reliability. Performance bugs related to BW and latency have been detected through the process, and it helps to design a performance-satisfied SOC. As a conclusion, A precise methodology for measuring the performance of BUS topology has been developed by directly comparing the performance results of the SystemC model and RTL.
Event Type
Front-End Design
TimeTuesday, July 11th2:00pm - 2:15pm PDT
Location2010, 2nd Floor
Front-End Design