Low power DAC sub-system for Digital Beam Forming Chip
DescriptionIn cutting edge satellite, terrestrial, and 5G wideband transmitters, there is a critical need to deploy highly efficient DACs (Digital-to-Analog Converters) with high sampling rates and high resolutions. The Analog Front End of a Digital Beam Forming system comprises multiple DACs driving a phased antenna array. There are hundreds of High Frequency DACs used per antenna comprising multiple chips thus making the power consumption of the DACs is a critical parameter that decides the feasibility of the entire RF system.
Process technology and standard cell optimizations will only shave off a small percentage of power. A major architectural innovation is proposed and implemented to significantly reduce the power.
The proposed architecture simplifies the method of programable latency introduction in a serializer data-path. The innovative design can accommodate infinite time shift while contemporary solutions are limited to increase in parallel data storage. A 10x power & 4.5x area reduction of DAC subsystem is achieved and a 16% power saving in total chip power is demonstrated.
Event Type
Front-End Design
TimeMonday, July 10th4:15pm - 4:30pm PDT
Location2010, 2nd Floor
Front-End Design