Presentation
Debug Accelerator & Performance Validator
DescriptionWith growing demand of high performance yet the smallest possible area, the complexity of any present day SOC is increasing many folds. In this time of high competition in time to market it becomes very essential and challenging to produce an SOC with-in a short time frame. Hence it becomes really important to have efficient and robust design verification flow knowing the fact that verification takes around 70% of the chip development cycle hence becomes prime factor of concern resulting in a number of cutting edge techniques efficiently reducing verification cycle with assured quality. In the same line this study presents a tool which helps in saving a lot of time in SOC verification by reducing debugging effort significantly which is one of the major concerns of any SOC DV engineer. This tool can result in up to 5x time saving in debugging giving a chance to invest this valuable time in brainstorming corner case verification scenarios enhancing DV quality and leaving no room for bug escapes. It also addresses another concern which deals with performance validation which is very crucial for any high performance centric SOCs. Study also presents some interesting results obtained post deployment of the tool.
Event Type
Front-End Design
TimeTuesday, July 11th2:15pm - 2:30pm PDT
Location2010, 2nd Floor
Front-End Design