Speeding-Up RISC-V GPGPU Accelerator using High-Bandwith Memory on FPGA
DescriptionAdvanced FPGA Accelerators like GPGPUs can greatly benefit from the high capacity and fast transfer rate of High-Bandwidth Memory (HBM). However, adding support for HBM on FPGA is not a trivial task and requires advanced domain expertise to understand how the HBM memory controller works and more importantly how to implement the software stack to communicate with the HBM device. In this work, we extended the memory system of the Vortex GPGPU processor with an HBM memory backend by leveraging Xilinx runtime API (XRT). The current implementation of Xilinx XRT is limited to supporting OpenCL kernel and simple user-managed RTL modules that implement a standard kernel interface. Our solution consists of both software and hardware changes to interface with XRT. We use the XRT MMIO API to control our custom GPU accelerator and we implemented an RTL wrapper to interface our GPU RTL with Xilinx XRT IP interface. Our design can be used as a reference for similar projects with other custom processors.
Event Type
Front-End Design
TimeTuesday, July 11th4:30pm - 4:45pm PDT
Location2010, 2nd Floor
Front-End Design