Presentation
CANCELED - Minimum System Voltage Prediction for Server Processor based on Machine Learning in Post Silicon
DescriptionCircuit Marginality Validation is a Post silicon validation domain which correlates minimum system voltages with the manufacturing measured Vmins based on Process, voltage, temperature and frequency parameters. CMV collects the system Vmin data and provides feedback to the Manufacturing team based on very limited number of parts covering the process variations(Slow, typical, fast units). CMV data collection is a time-consuming process. One sample might take 6-8 weeks of time per test cycle. Hence there is a need to Optimize such time consumptions in redoing the similar exercise during multiple more test cycles. Also there is a need to provide coverage for Multiple more samples to give a better feedback and accurate results to Manufacturing. The proposed solutions enables System Vmin prediction based on AI model which will help time and resource optimizations and ensure system Vmin predictions way ahead of the actual executions are done. This shall also ensure Vmin results for More quantity of units to provide better quality feedback to the Manufacturing team. The Vmin Prediction is based on Domain Frequency, Intra die process variation, Manufacturing tester Vmin data and current CMV measurements. Any productions flaws on the sample can be caught easily when actual measurements are drastically deviating predicted voltages.
Event Type
Front-End Design
TimeTuesday, July 11th3:45pm - 4:00pm PDT
Location2010, 2nd Floor
Front-End Design
RISC-V