Presentation
Chiplet and Die-to-Die (D2D) Interface Interoperability—How to Accelerate the Path to an Open Ecosystem
DescriptionHeterogeneous chiplet-based designs enable the integration of die from multiple process nodes and vendors into a single-package product. This emerging technology is needed to boost compute power while building cost effective systems for High-Performance Computing (HPC), Artificial Intelligence (AI) and Machine-Learning System On Chip (ML SOC) products. In this paper, we introduce industry efforts to accelerate the chiplet ecosystem and the key metrics used to ensure design and technology interoperability between chiplet die coming from different sources.
Today, most chiplet-based logic products are based on closed interfaces and integrate die from a single company, thereby creating silos of inter-company technical specifications, workflows, and business requirements.
It is an obvious choice for the industry to demand more with regards to chiplet integration and have reason to accelerate its adoption. Efforts to build an ecosystem for chiplets have been materialized through the standardization of Die-to-Die (D2D) IP subsystem interfaces for plug-in solutions (thereby addressing interoperability at different levels) by the Open Domain-Specific Architecture (ODSA) Working Group, the Optical Internetworking Forum (OIF), and most recently, the Universal Chiplet Interconnect Express™ (UCIe™) .
The chiplet industry has placed more emphasis on the newer UCIe specification due to its completeness on what is required for an open D2D interface; this translates into new opportunities—as well as challenges—in testing standards compliance for multi-chiplet products.
The opportunity to leverage established protocol interfaces and practices readily available by product designers means that those who are currently integrating interfaces such as PCIe and CXL protocols can simply reuse proven methodologies. While the challenge in enabling a high degree of interoperability using standard defined form factors and test structures when integrating different chiplets across multiple vendors is not to be underestimated, this enablement of interface/practice democratization on the concept of chiplet product will be invaluable.
This paper reviews recent developments in chiplet interoperability metrics (including protocol layer definitions and physical interfaces) by leveraging current industry work on PCIe and CXL protocols and High-Bandwidth Memory (HBM) interfaces. This paper also discusses the extension of chiplets to test products based on open D2D interfaces.
After defining the path towards protocol and electrical interface compliance, product designers will then have to address packaging and test challenges which will be inherent when integrating chiplets from multiple vendors. Thus, this paper further discusses how the work in HBM interfaces and Design For Test (DFT) scan standards for ‘system-in-package' devices can be extended to heterogenous chiplet-based products.
Lastly, this paper provides the list of cross-functional interoperability metrics that ‘system-in-package' design teams must consider when integrating chiplets in an open-system, and also highlights the areas of improvement that must be addressed in the current interface standard environment for chiplets.
Today, most chiplet-based logic products are based on closed interfaces and integrate die from a single company, thereby creating silos of inter-company technical specifications, workflows, and business requirements.
It is an obvious choice for the industry to demand more with regards to chiplet integration and have reason to accelerate its adoption. Efforts to build an ecosystem for chiplets have been materialized through the standardization of Die-to-Die (D2D) IP subsystem interfaces for plug-in solutions (thereby addressing interoperability at different levels) by the Open Domain-Specific Architecture (ODSA) Working Group, the Optical Internetworking Forum (OIF), and most recently, the Universal Chiplet Interconnect Express™ (UCIe™) .
The chiplet industry has placed more emphasis on the newer UCIe specification due to its completeness on what is required for an open D2D interface; this translates into new opportunities—as well as challenges—in testing standards compliance for multi-chiplet products.
The opportunity to leverage established protocol interfaces and practices readily available by product designers means that those who are currently integrating interfaces such as PCIe and CXL protocols can simply reuse proven methodologies. While the challenge in enabling a high degree of interoperability using standard defined form factors and test structures when integrating different chiplets across multiple vendors is not to be underestimated, this enablement of interface/practice democratization on the concept of chiplet product will be invaluable.
This paper reviews recent developments in chiplet interoperability metrics (including protocol layer definitions and physical interfaces) by leveraging current industry work on PCIe and CXL protocols and High-Bandwidth Memory (HBM) interfaces. This paper also discusses the extension of chiplets to test products based on open D2D interfaces.
After defining the path towards protocol and electrical interface compliance, product designers will then have to address packaging and test challenges which will be inherent when integrating chiplets from multiple vendors. Thus, this paper further discusses how the work in HBM interfaces and Design For Test (DFT) scan standards for ‘system-in-package' devices can be extended to heterogenous chiplet-based products.
Lastly, this paper provides the list of cross-functional interoperability metrics that ‘system-in-package' design teams must consider when integrating chiplets in an open-system, and also highlights the areas of improvement that must be addressed in the current interface standard environment for chiplets.
Presenter
Event Type
IP
TimeWednesday, July 12th1:45pm - 2:00pm PDT
Location2012, 2nd Floor
IP
RISC-V