Weak Link Detection in Memory Periphery using Design Robustness Analysis
DescriptionFor high density memories, periphery design is mostly done in full custom or manual design approach to ensure minimum area usage. Such designs are vulnerable to errors, e.g., under-sizing of logical stages resulting in non-optimum delay/variations. Memory design involves rigorous statistical validations with respect to memory cells, that comprises of minimum device features. However, periphery devices that constitute address decoding, data input, row/column selection circuits, internal clock generator, read/write assist circuits and few other blocks do not use minimum size devices but subjected to larger logical depth and loads. Such designs being prone to large delay variations due to inadequate sizing also affects critical memory timings. In this work, we have analyzed a memory (SRAM) instance having 16384 words and 80 bits in 40nm CMOS technology.
Because of large size of memory IP, running Monte Carlo on the full IP for say 1M samples (to capture >4 sigma variation) is not practically feasible. Hence, there is a need for a new approach to identify wrongly sized transistors. In this paper, we will discuss about Design Robustness Analysis (DRA) tool built into PrimeSim AVA (Advanced Variation Analysis) technology from Synopsys. This technology uses a machine-learning based approach clubbed with targeted variability simulations to identify these weak devices. We were able to detect multiple weak points in memory periphery that needed designer's attention to correct them. We have illustrated one of the important design aspects that required correction.
TimeTuesday, July 11th1:45pm - 2:00pm PDT
Location2012, 2nd Floor