Digital Design Flow for Area-Constrained IPs Using Custom Non-standard IEEE-754 Format​
DescriptionThe design of complex algorithms in analog-on-top products is increasing and is challenging since technology node is driven by analog specifications. Digital area is bound by package and overall cost.

Therefore, finding the best trade-off among accuracy and area can require long design time.

Most sensor applications have data rate in the order of Hz, while internal system clock is usually in the order of MHz, so serialization techniques can be exploited to reduce area.

A design exploration flow based on non-standard floating-point formats and parametric arithmetical submodules has been developed. Their customization can be performed on precision and serialization in terms of clock cycles.

Firstly, the algorithm is written in python using single precision floating point, setting a referral accuracy. Secondly, the algorithm is re-written using the parametric submodules, where the parameters are number of clock cycles, significand and exponent size of the custom format.

Given max accuracy loss or latency as input criteria, an automated tool generates parameters to be applied to RTL code of float point unit and arithmetical submodules.

With this flow the time required to design complex embedded algorithms is hugely reduced, allowing us to tailor the design to the applications as per customer needs.
Event Type
TimeMonday, July 10th3:45pm - 4:00pm PDT
Location2012, 2nd Floor