Presentation
Delivering on RISC V's Promise to Give Designers Freedom to Innovate – What's Needed?
DescriptionThe RISC-V instruction set architecture (ISA) open standard has accelerating momentum in the semiconductor community. This is due to the open nature of the ISA, enabling users to build domain specific processors that can help to differentiate products. Is this momentum built on real SoCs going to production? What is needed to develop a RISC-V based SoC? How mature is the specification? Is RISC-V ready for prime time?
This panel, from various areas in the RISC-V community / ecosystem from fab through to end user, will try to address these questions and more, and provide their perspectives on the readiness of RISC-V, and the path to RISC-V based silicon.
This panel, from various areas in the RISC-V community / ecosystem from fab through to end user, will try to address these questions and more, and provide their perspectives on the readiness of RISC-V, and the path to RISC-V based silicon.
Event Type
IP
TimeWednesday, July 12th10:30am - 12:00pm PDT
Location2012, 2nd Floor
IP
RISC-V