Presentation
Comprehensive Validation Solution for Silicon IP&Library
DescriptionIP & Libraries are a key contributor to innovation in the semiconductor industry today. As the complexity and scale of silicon designs increase, so does design and validation time. Design IP enables modularization and re-use of design components, so that designers can leverage already-existing components as a baseline to accelerate design schedules. Therefore, it is not surprising that the usage of design IP has grown rapidly in the past decade.
However, like any component of a silicon design, IP may contain errors which are difficult to detect due to the vast number of views and values contained in an IP & library. Traditional methods used to validate and regress IP's and Libraries have remained largely unchanged. However, with shrinking technology nodes, design complexities, and the need to model the advanced node effects to account for variations in circuit performance, there is a necessary need for a thorough library validation process. Validation and regression of these complex and large design views files is a challenging task and poses a significant threat to successful rtl2gds flow and even silicon failures if the errors are not detected and fixed in time.
Traditional IP & Library validation tools that provide static, rule-based checks can verify the syntax of the views, but given the complexity and large volume of characterized data at the advanced technology nodes, these checks are no longer sufficient. There is a need for a sophisticated IP QA system that not only performs syntactical checks but also detects any data outliers, consistency and modelling issues that could potentially cause failures in the later stages of the flow. This paper describes innovative, scalable and comprehensive methodology to significantly speed up library validation runtime to achieve better quality libraries, shorter and predictable production schedules and improved power, performance, area (PPA) and yield for silicon designs. These methodology and implemented solution can also bridge the gap that exists today between what design engineers require for signoff and what library teams can deliver.
However, like any component of a silicon design, IP may contain errors which are difficult to detect due to the vast number of views and values contained in an IP & library. Traditional methods used to validate and regress IP's and Libraries have remained largely unchanged. However, with shrinking technology nodes, design complexities, and the need to model the advanced node effects to account for variations in circuit performance, there is a necessary need for a thorough library validation process. Validation and regression of these complex and large design views files is a challenging task and poses a significant threat to successful rtl2gds flow and even silicon failures if the errors are not detected and fixed in time.
Traditional IP & Library validation tools that provide static, rule-based checks can verify the syntax of the views, but given the complexity and large volume of characterized data at the advanced technology nodes, these checks are no longer sufficient. There is a need for a sophisticated IP QA system that not only performs syntactical checks but also detects any data outliers, consistency and modelling issues that could potentially cause failures in the later stages of the flow. This paper describes innovative, scalable and comprehensive methodology to significantly speed up library validation runtime to achieve better quality libraries, shorter and predictable production schedules and improved power, performance, area (PPA) and yield for silicon designs. These methodology and implemented solution can also bridge the gap that exists today between what design engineers require for signoff and what library teams can deliver.
Event Type
IP
TimeMonday, July 10th2:30pm - 2:45pm PDT
Location2012, 2nd Floor
IP
RISC-V