Lightning Talk: High Fidelity Benchmarking of Interposer Material Choices Using 2.5D Design Tools
DescriptionGlass interposer offers low-cost options to embed chiplets directly inside the substrate itself. This enables 3D stacking configuration between the embedded dies and the conventional flip-chip dies mounted directly on top. Furthermore, the interconnect pitch and through-glass-via (TGV) diameter in glass are becoming comparable to their counterparts in silicon. In this work, we investigate the power, performance, area (PPA), signal integrity (SI), and power integrity (PI) benefits of 3D stacking enabled by glass interposer in comparison with silicon interposer. Our research is enabled by chiplet/package co-design tools that produce high fidelity graphic data system (GDS) layouts of the chiplets, their routing in interposers, and sign-off quality simulation results.
TimeWednesday, July 12th10:30am - 10:40am PDT
Location3008, 3rd Floor
Design Methodologies for System-on-Chip and 3D/2.5D System-in Package