Presentation
Lightning Talk: Scaling Up Quantum Compilation -- Challenges and Opportunities
DescriptionThe past decade witnessed exciting advances in quantum computing (QC) platforms. For example, superconducting qubit systems of over a hundred qubits have been developed and are now commercially available. Trapped ion systems in long chains or quantum charge-coupled device (CCD) architectures have also been developed, reaching very low gate errors Recently, neutral atoms trapped in arrays of optical tweezers emerged as a very promising experimental platform with hundreds of qubits at room temperature for programmable quantum simulations and quantum computation. With IBM’s recent announcement ofthe plan for building a 100,000-qubit quantum processing unit (QPU). There is a strong need to scale up the capacity and performance of quantum compilation tools to match the rapid advances of quantum hardware. Quantum compilation for a given quantum program and QPU typically goes through two stages: (i) logic synthesis, which transforms a quantum program into a quantum circuit using only the native gate set on a given quantum computer, and (ii) layout synthesis, which performs gate scheduling and placement with possible insertion of SWAP gates while conforming to the connectivity constraint of the chosen QPU. In the noisy intermediate-scale quantum (NISQ) era, the compiler optimization objective is to minimize the resulting circuit depth or the total number of SWAP gates, as they both affect the circuit fidelity. A large part of this paper focuses on the layout synthesis step as it is often the computation bottleneck in the compilation process (involving both spatial and temporal decisions). We discuss possible optimizations beyond layout synthesis at the end.
Event Type
Research Manuscript
TimeTuesday, July 11th10:30am - 10:40am PDT
Location3003, 3rd Floor
Design
Quantum Computing