Presentation
Lightning Talk: Feasibility Checking for Advanced Packaging
SessionRoute Me if You Can!
DescriptionDue to the physical limitation, the cost and overhead of chip shrinking becomes more and more significant. Therefore,
the criticality of advanced packaging walks into the spotlight to advance design scaling. Package-level 3D-IC methodologies provide a solution to improve the performance and scalability for the systems with acceptable manufacturing cost. In addition, chip-package-board codesign provides another dimension to boost the performance, power, and area for the systems. To enable a global solution for system planning, advanced packaging plays an important role. In tradition, design houses or system companies rely on experienced system designers to iterate between chip, package, and board in the early planning stage to decide I/O bump assignment, component placement, the number of routing layers, and etc for package design. The planning process is time consuming and knowledge intensive. If there are issues relate to routability or performance emerging in the later stages, the cost of re-design will be significant. Therefore, EDA companies propose system planning or prototyping solutions to identify the issues in the early stages to speed up design cycles. There are some important components to enable system planning for advanced packaging design.
- Global planning: Read given design environment and specs, tool can provide automatic or semi-auto solutions to
quickly plan component placement and I/O assignment to co-design chip, package, and board.
- Feasibility checking – To evaluate whether the planning solution can be implemented, feasibility checking is very
important. Given a placed package design, an auto router is required to honor manufacturing rules and quickly realize
connections with minimal violations. Then, designers can check the routing result to revise the number of routing
layers, I/O assignment, bump pitch, and the placement of components.
- Simulation – Execute quick timing, power, thermal, and mechanical simulation to capture the potential performance
and manufacturing issues for the routed solution identified by feasibility checking stage. If any issue is found,
feedback the issue to the early stages to refine the design.
the criticality of advanced packaging walks into the spotlight to advance design scaling. Package-level 3D-IC methodologies provide a solution to improve the performance and scalability for the systems with acceptable manufacturing cost. In addition, chip-package-board codesign provides another dimension to boost the performance, power, and area for the systems. To enable a global solution for system planning, advanced packaging plays an important role. In tradition, design houses or system companies rely on experienced system designers to iterate between chip, package, and board in the early planning stage to decide I/O bump assignment, component placement, the number of routing layers, and etc for package design. The planning process is time consuming and knowledge intensive. If there are issues relate to routability or performance emerging in the later stages, the cost of re-design will be significant. Therefore, EDA companies propose system planning or prototyping solutions to identify the issues in the early stages to speed up design cycles. There are some important components to enable system planning for advanced packaging design.
- Global planning: Read given design environment and specs, tool can provide automatic or semi-auto solutions to
quickly plan component placement and I/O assignment to co-design chip, package, and board.
- Feasibility checking – To evaluate whether the planning solution can be implemented, feasibility checking is very
important. Given a placed package design, an auto router is required to honor manufacturing rules and quickly realize
connections with minimal violations. Then, designers can check the routing result to revise the number of routing
layers, I/O assignment, bump pitch, and the placement of components.
- Simulation – Execute quick timing, power, thermal, and mechanical simulation to capture the potential performance
and manufacturing issues for the routed solution identified by feasibility checking stage. If any issue is found,
feedback the issue to the early stages to refine the design.
Event Type
Research Manuscript
TimeTuesday, July 11th3:30pm - 3:40pm PDT
Location3008, 3rd Floor
EDA
Physical Design and Verification