Design Considerations and Tradeoffs for 2.5D Chiplet Solutions
DescriptionThe interest in chiplets has increased dramatically to expand performance, mitigate rising mask costs, and enable resuse. Initially, chiplets, 2.5D, and 3D solutions were reserved for the knighted few, Intel with its Foveros technology, AMD's CCD for its Zen CPU line, and Broadcom with its Spectrum-4. Now, mid- and small-cap companies alike are targeting chiplets for economic and performance reasons. This panel will examine and discuss product decisions, such as die-to-die interface technology, packaging considerations, and verification methodologies through EDA, hyperscaler, clocking, and packaging lens.
Before entering the panel discussion, the moderator will provide the audience with a brief history of 2.5D and D2D solutions while defining key terms to provide level grounding for the audience. The panel will discuss:
• What factors are driving 2.5D adoption? How is this adoption changing your segment?
• What tools, flow, methodology, and architectural considerations are required for modern 2.5D designs?
• What are the tradeoffs for system designers to consider when comparing BoW vs. UCIe vs. other solutions? What applications best suited for each technology?
The panel will end with forward-looking statements on the future of 2.5D and 3D solutions. The panelists will explore possible improvements in methodology, tools, and technology.
DAC Pavilion Panel
TimeTuesday, July 11th2:00pm - 2:45pm PDT
LocationDAC Pavilion, Level 2 Exhibit Hall