Presentation
Bumblebee: A MemCache Design for Die-stacked and Off-chip Heterogeneous Memory Systems
DescriptionEmerging die-stacked memories can provide higher bandwidth than traditional off-chip DRAM and serve as an off-chip DRAM cache or part of OS-visible memory (POM). This paper presents Bumblebee, a new hybrid memory architecture combining the advantages of both DRAM cache and POM. The ratio of DRAM cache to POM is adjustable in real time to better exploit both temporal and spatial locality benefits for different memory access patterns. Our evaluations indicate at least 35.2% performance improvement and 10.9% ∼ 20.1% less memory dynamic energy consumption for Bumblebee over state-of-the-art designs, as well as orders of magnitude less metadata storage space.
Event Type
Research Manuscript
TimeWednesday, July 12th11:25am - 11:40am PDT
Location3006, 3rd Floor
Design
SoC, Heterogeneous, and Reconfigurable Architectures