Presentation
Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System
DescriptionWe propose a mechanism for efficient management of memory accesses to a multi-retention LLC, where based on the initial requester (CPU or GPU) cache blocks are allocated in the high (CPU) or low (GPU) retention zone. Furthermore, blocks that are yet to expire are either refreshed (CPU) or written back (GPU). In addition, ARMOUR evicts CPU blocks having estimated short liveness, which further improves cache performance by reducing cache pollution. Our evaluation shows that ARMOUR improves average performance by 28.9% compared to baseline STT-RAM LLC and reduces the energy-delay product (EDP) by 74.5% compared to an iso-area SRAM LLC.
Event Type
Research Manuscript
TimeTuesday, July 11th11:25am - 11:40am PDT
Location3006, 3rd Floor
Design
RISC-V
SoC, Heterogeneous, and Reconfigurable Architectures