Presentation
Glass Interposer Integration of Logic and Memory Chiplets: PPA and Signal/Power Integrity Benefits
SessionCircuit Design Potpourri
DescriptionGlass interposers enable 3D stacking between the chiplets embedded into the substrate and the ones stacked directly on top, which is not possible in silicon. In this work, we demonstrate the benefits of such stacking in glass interposers over silicon in terms of key system-level metrics including area, wirelength, signal, power, and thermal integrity. We achieve this goal with GDS layouts of both chiplets and interposers and sign-off simulations. Our experiments show that glass offers 2.6X area, 21X wirelength, 65.4% signal integrity, and 10X power integrity improvement over silicon at the cost of 45.9% increase in temperature.
Event Type
Research Manuscript
TimeTuesday, July 11th11:10am - 11:25am PDT
Location3010, 3rd Floor
Design
AI/ML, Digital, and Analog Circuits