Presentation
Restructure-Tolerant Timing Prediction via Multimodal Fusion
SessionAll Routes to Timing Closure
DescriptionFast and accurate pre-routing timing prediction is crucial in the very-large-scale integration (VLSI) design flow. Existing machine learning (ML)-assisted pre-routing timing evaluators neglect the impact of timing optimization, which may render their approaches impractical in real circuit design flows. To model the impact of timing optimization, we propose an endpoint embedding framework that integrates netlist-layout information via multimodal fusion. An end-to-end flow is further developed for pre-routing prediction on optimization-affected sign-off timing metrics. Comprehensive experiments on large-scale RISC-V designs with advanced 7-nm technology node demonstrate the superiority of our model compared to the SOTA pre-routing timing evaluator.
Event Type
Research Manuscript
TimeTuesday, July 11th1:55pm - 2:10pm PDT
Location3002, 3rd Floor
EDA
RISC-V
Timing and Low Power Design