Presentation
LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage
DescriptionTo reduce memory design iterations, engineers design layouts by predicting physical metrics from floorplans. However, it is difficult to predict the metrics accurately, because floorplans are designed with approximate block layout sizes without layouts. We propose LayNet, which accurately predicts block layout sizes for reliable floorplans. We construct weighted circuit graphs by formulating the possibility that elements are adjacent in layout, and predict block sizes with graph neural networks. LayNet shows state-of-the-art performances on 5000 industrial memory circuits. Specifically, we reduce mean absolute percentage errors by 68.26% and 10.34% for manually and semi-automatically generated layouts, respectively, compared to conventional approaches.
Event Type
Work-in-Progress Poster
TimeTuesday, July 11th6:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security