Presentation
NoNL-DFR: New Model of Digital Delayed Feedback Reservoir without Nonlinear Elements
DescriptionA delayed feedback reservoir (DFR) is suitable for hardware implementation because of its simple structure consisting of a nonlinear element and a feedback loop. However, implementation using analog circuits requires a DAC and ADC, and the feedback delay reduces throughput. Furthermore, conventional digital implementations involve divisions and power calculations, which increase power consumption. This paper proposes NoNL-DFR, a succinct digital DFR implementation without nonlinear elements. Unlike existing implementations, NoNL-DFR uses neither DAC nor ADC. In addition, we eliminated expensive calculations. Implementations on a FPGA confirmed increased throughput with reduced power consumption compared to existing implementations with no loss of accuracy.
Event Type
Work-in-Progress Poster
TimeWednesday, July 12th6:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security