Improving Standard-Cell Design Flow using Factored Form Optimization
DescriptionFactored form is a multi-level representation of a Boolean function that readily maps into CMOS technology. In particular, the number of literals of a factored form correlates well with the number of transistors. This paper focuses on developing techniques for minimizing the total factored form literals count in an and-inverter graph. The proposed methods lead to reduced literal counts compared to traditional methods. Experiments show that applying these methods helps reduce area after technology mapping by 2.6%. It is expected that deploying these techniques as part of an industrial standard-cell design flow will dramatically reduce design costs and power consumption.
TimeTuesday, July 11th11:10am - 11:25am PDT
Location3002, 3rd Floor
RTL/Logic Level and High-level Synthesis