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Design Automation for Cryogenic CMOS Circuits
DescriptionApplications like quantum computing and infra-red imaging require large-scale cryogenic CMOS circuits. Currently, there is no design automation flow for such circuits. Firstly, there is limited transistor data for cryogenic operation. Then, no cryogenic standard cell library is available which describes power and delay of the standard cells. Lastly, there is no synthesis which suits the needs of cryogenic CMOS operating in cryogenic chambers with severe restrictions on cooling power. This work aims to provide a calibrated transistor model for 5nm FinFET, the first cryogenic standard cell library and first cryogenic-aware synthesis to enable a cryogenic design automation flow.
Event Type
Research Manuscript
TimeWednesday, July 12th3:40pm - 3:55pm PDT
Location3006, 3rd Floor
Topics
Design
Keywords
Emerging Device Technologies