Presentation
PATRONoC: Parallel AXI Transport Reducing Overhead for Network-on-Chips targeting Multi-Accelerator DNN Platforms at the Edge
DescriptionEmerging deep neural network (DNN) applications require high performance multi-core hardware acceleration with large data bursts. Classical network-on-chips (NoC) use serial packet-based protocols suffering from significant protocol translation overheads towards the endpoints. This paper proposes PATRONoC, an open-source fully AXI-compliant NoC fabric to better address the specific needs of multi-core DNN computing platforms. Evaluation of PATRONoC in 2D-mesh topology shows 34% higher area-efficiency compared to a state-of-the-art classical NoC at 1GHz. PATRONoC's throughput outperforms a baseline NoC by 2-8X on uniform random traffic and provides a high aggregated throughput of up to 350 GiB/s on synthetic and DNN workload traffic.
Event Type
Research Manuscript
TimeTuesday, July 11th3:40pm - 3:55pm PDT
Location3006, 3rd Floor
Design
AI/ML System and Platform Design