Fine-Grained QoS Control via Tightly-Coupled Bandwidth Monitoring and Regulation for FPGA-based Heterogeneous SoCs
DescriptionEmbedded systems are increasingly adopting heterogeneous templates integrating hardware accelerators and application-specific processors, which poses novel challenges. In particular, the complex main memory hierarchy, hinders an accurate control of task activities in Commercial Off-the-shelf (COTS) Heterogeneous System on Chips (HeSoCs).
To address this problem, bandwidth regulation approaches based on monitoring and throttling are widely adopted. Existing solutions however are often coarse-grained, limiting the control over computing engines activities. On the other hand, the fine-grained ones are platform-dependent. In this paper we propose an innovative, fine-grained, and platform-independent approach that can accurately control main memory bandwidth usage in a FPGA-based HeSoCs.
TimeTuesday, July 11th11:10am - 11:25am PDT
Location3006, 3rd Floor
SoC, Heterogeneous, and Reconfigurable Architectures