Presentation
HTVM: Efficient Neural Network Deployment On Heterogeneous TinyML Platforms
DescriptionOptimal deployment of deep neural networks (DNNs) on state-of-the-art Systems-on-Chips (SoCs) is crucial for tiny machine learning (TinyML) at the edge. The complexity of these SoCs makes deployment non-trivial, as they typically contain multiple heterogeneous compute cores with limited, programmer-managed memory to optimize latency and energy efficiency.
We propose HTVM – a compiler that merges TVM with DORY to maximize the utilization of heterogeneous accelerators and minimize data movements. HTVM allows deploying the MLPerf™ Tiny benchmarking suite on Diana, an SoC with a RISC-V CPU, and digital and analog compute-in-memory AI accelerators, at 116x improved performance over plain TVM deployment.
We propose HTVM – a compiler that merges TVM with DORY to maximize the utilization of heterogeneous accelerators and minimize data movements. HTVM allows deploying the MLPerf™ Tiny benchmarking suite on Diana, an SoC with a RISC-V CPU, and digital and analog compute-in-memory AI accelerators, at 116x improved performance over plain TVM deployment.
Event Type
Research Manuscript
TimeThursday, July 13th4:40pm - 4:55pm PDT
Location3006, 3rd Floor
Embedded Systems
RISC-V
Embedded Software