Presentation
Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits
SessionBeyond Moore is Cool
DescriptionWe address the thermal challenge of ultra-dense 3D (e.g., monolithic 3D) chips with stacked high-power computing engines. We present a thermal scaffolding approach achieved through (1) new Back End of Line (BEOL)-compatible dielectric materials for simultaneous high thermal conductivity and low dielectric constant, (2) new 3D physical co-design of BEOL dielectrics with thermal BEOL metal structures, and (3) experimentally demonstrated advances in external heat removal. Scaffolding of an ultra-dense 3D 7nm systolic array physical design is shown to decrease peak temperatures by 10.2×. This enables 4× more stacked layers of heavy-duty compute at low area and delay penalty.
Event Type
Research Manuscript
TimeWednesday, July 12th4:10pm - 4:25pm PDT
Location3006, 3rd Floor
Design
Emerging Device Technologies