Presentation
CANCELED - Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions
DescriptionWhile conventional logic synthesis aggressively optimizes the number of nodes in logic networks, this trope does not incorporate additional costs caused by inverters and interconnects in the form of wire segments, signal splitters, and crossings as imposed by beyond-CMOS circuit implementations such as photonic crystals, SiDBs, AQFP, QCA, and NML. In this paper, we propose a scalable technology mapping algorithm that captures those unconventional costs by utilizing subcircuit databases that are obtained by applying technology-aware exact physical design techniques. Hereby, we overcome the substantial quality loss that previously inevitably occurred when generating beyond-CMOS circuit layouts from conventionally optimized logic networks.
Event Type
Work-in-Progress Poster
TimeWednesday, July 12th6:00pm - 7:00pm PDT
LocationLevel 2 Lobby
AI
Autonomous Systems
Cloud
Design
EDA
Embedded Systems
RISC-V
Security