Presentation
Accelerating Sparse Attention with a Reconfigurable Non-volatile Processing-In-Memory Architecture
DescriptionAttention-based neural networks have shown superior performance in a wide range of tasks.
From the hardware perspective, non-volatile processing-in-memory~(NVPIM)-based architecture shows its great potential to accelerate the dense model.
We aim to improve the mapping efficiency for the sparse workloads by introducing two vector-based primitives with a reconfigurable NVPIM bank.
Our evaluation result shows that, over previous NVPIM
accelerators, our design could deliver up to 12.36× performance
improvement and 3.4× energy efficiency improvement on a range
of vision and language tasks
From the hardware perspective, non-volatile processing-in-memory~(NVPIM)-based architecture shows its great potential to accelerate the dense model.
We aim to improve the mapping efficiency for the sparse workloads by introducing two vector-based primitives with a reconfigurable NVPIM bank.
Our evaluation result shows that, over previous NVPIM
accelerators, our design could deliver up to 12.36× performance
improvement and 3.4× energy efficiency improvement on a range
of vision and language tasks
Event Type
Research Manuscript
TimeWednesday, July 12th4:55pm - 5:10pm PDT
Location3004, 3rd Floor
Design
In-memory and Near-memory Computing Circuits