Algorithms and Hardware for Efficient Processing of Logic-based Neural Networks
DescriptionRecent efforts to improve the performance of neural network (NN) accelerators that meet today's application requirements have given rise to a new trend of logic-based NN inference relying on fixed-function combinational logic (FFCL). This paper presents an innovative optimization methodology for compiling and mapping NNs utilizing FFCL into a Boolean processor. The presented method maps FFCL blocks to a set of Boolean functions where Boolean operations in each function are mapped to high-performance, low-latency, parallelized processing elements. Graph partitioning and scheduling algorithms are presented to handle FFCL blocks that cannot straightforwardly fit the Boolean processor.
Event Type
Research Manuscript
TimeWednesday, July 12th4:25pm - 4:40pm PDT
Location3010, 3rd Floor
AI/ML Architecture Design