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A Comprehensive Automated Exploration Framework for Systolic Array Designs

DescriptionThere is a plethora of previous works on the performance tuning of systolic arrays but are usually based on oversimplified assumptions like considering only divisors for loop tiling or pruning based on off-chip data communication to reduce the design space. In this paper, we present a comprehensive design space exploration tool named Odyssey for systolic array optimization. Odyssey results show that limiting to divisors for loop tiling leads to a 39% performance loss, and pruning based on off-chip data movement results in a 45% performance loss. We tested Odyssey on a number of examples and validated with execution on FPGAs.

Authors

Suhail Basalama

University of California, Los Angeles

Jie Wang

University of California, Los Angeles

Jason Cong

University of California, Los Angeles

Event Type

Research Manuscript